This invention relates to semiconductor devices, and more particularly to substrate bias generator circuits for dynamic read/write memory devices or the like.
Substrate bias generator circuits for MOS LSI devices have been costructed as shown in U.S. Pat. No. 4,115,710, issued to Perry W. Lou, U.S. Pat. No. 4,494,223, issued Jan. 15, 1985 to G. R. M. Rao and C. N. Reddy, or Ser. No. 512,078, filed July 8, 1983 by Hashimoto & Reddy, assigned to Texas Instruments. The very high density dynamic RAMs now being designed have more stringent requirements, however. The power dissipation during both operating and standby modes is more critical, and since CMOS structures are used latch-up becomes a problem at power-on.
It is the principal object of this invention to provide an improved substrate bias generator circuit for a semiconductor device such as a dynamic RAM. Another object is to provide a charge pump circuit that is more efficient and operates faster. Another objet is to provide a substrate bias generator that reduces operating and standby power dissipation.